Last updated on December 8th, 2022 at 02:03 pm
To do this, you need to create a new generation transistor
Samsung intends to develop a 3-nanometer process technology in 2022. For this process, technology will have to significantly change the design of the transistor, in fact creating a new generation transistor.
Samsung expects to develop a 3-nanometer process technology in 2022
Samsung is currently working on Gate-All-Around FET (GAAFET) technology, which will provide much better channel control and prevent leakage while downsizing. However, for 3 nm, the next step is necessary. The South Korean manufacturer spoke about the corresponding development called Multi Bridge Channel FET or MBCFET. It will be used in 3-nanometer chips.
Note that MCBFET is a special case of the more general approach adopted by GAAFET. At the same time, MCBFET, according to Samsung, will reduce energy consumption by half and increase speed by 30%. The area occupied by the transistor will decrease by 45%. It is worth clarifying that the comparison is carried out with a certain 7-nanometer process technology, probably Samsung technology, built using FinFET. An interesting feature of the MCBFET is the ability to stack transistors on top of each other in order to use even less space compared to a conventional FinFET. You can also change the width of the transistors in the stack, adapting it to certain technical requirements, for example, in terms of power consumption or speed.
