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Intel showed the structure of Tiger Lake processors: a third of the chip is reserved for integrated graphics

Intel showed the structure of Tiger Lake processors: a third of the chip is reserved for integrated graphics

Intel Tiger Lake mobile processors, which will be announced on September 2, were described in sufficient detail at the Intel Architecture Day 2020 event. Intel announced additional revelations about them at the Hot Chips conference. The image of the Tiger Lake crystal allowed us to understand what the developers’ priorities were when creating processors.

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The official image of the Tiger Lake crystal was refined by a Locuza enthusiast, after which it received graphic and text annotations. We emphasize that the conditional distribution of functional blocks in the above illustration was proposed by a private enthusiast, therefore it may contain inaccuracies. A mystery, for example, remains the purpose of the two areas adjacent to the graphics subsystem, which are highlighted in cool green.

Tiger Lake processors, we recall, should be equipped with Xe-LP (Gen12) graphics, whose performance will surpass its predecessor twice. Crystal Tiger Lake had to allocate almost a third of its area for integrated graphics. It has 96 execution units, supports displaying images on four monitors with 4K resolution simultaneously. Implementing support for four Thunderbolt 4.0 ports also required certain sacrifices in terms of die area. At the same time, USB 4.0 is supported.

The memory controller of Tiger Lake processors is quite versatile. It supports DDR4-3200 memory up to 64 GB, LPDDR4X-4267 memory up to 32 GB, and in the future, it will support LPDDR5-5400 memory up to 32 GB. The information stored in memory is fully encrypted.

In general, one of the important changes in Tiger Lake processors is the increase in the amount of cache memory of the second and third levels compared to their predecessors. At the second level, the cache size increased from 512 KB to 1.25 MB per core, at the third – from 8 to 12 MB in total. The cache memory now works according to a non-inclusive scheme, there is no need to store a copy of the second-level cache data in the third-level cache.

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