First-generation 5nm products are already in production. They provide a 15% increase in transistor speed compared to 7nm products or can reduce power consumption by 30% while maintaining the same performance. At the same time, the density of the transistors has increased by 1.8 times compared to the 7-nm technical process.

The second generation of the 5nm N5P process will make it to mass production next year. It will raise the speed of transistors by 5% or will reduce power consumption by ten percent. The so-called 4-nm technical process (N4), which will become a cheaper alternative to 3-nm, is also prepared from TSMC. Pilot production of 4nm products will start in the fourth quarter of next year, mass production only in 2022.

The development of the 5nm process technology in terms of defect density is now progressing a quarter ahead of the schedule inherent in 7nm technology. If we talk about the 3nm process technology performed by TSMC, then the company is going to rely on the already proven FinFET structures, in contrast to Samsung, which is experimenting with so-called GAA transistors (gate-all-around, “completely surrounded by gates”).

The 3 nm process technology will increase the speed of transistors by 10-15% relative to 5 nm, or reduce power consumption by 25-30% with the same performance. The density of the transistors should increase by 1.7 times. SRAM memory cells during the transition to a 3-nm process technology will increase the density of the elements by 20%, analog components may be limited to an increase in density by 1.1 times.

TSMC is going to conquer the era “after 3 nm” with the help of alternative materials, not just silicon. Carbon nanotubes and nanowires should be used in this area. TSMC has been developing in this direction since 2019, but the conservatism regarding the 3-nm process technology suggests that the company will only introduce the most proven and reliable solutions in mass production.