AMD develops an active interchiplet bus with on-board cache for GPUs
AMD has filed a patent describing a feature of the GPU chipset design (multi-die). A new patent called Active Bridge Chiplet With Integrated Cache describes an active bus with integrated cache memory. We can assume that we are talking about the evolution of the Infinity Cache technology, which first appeared in the Radeon RX 6000 series video cards.
AMD’s idea is to assign to the interface connecting the individual GPU chiplets, including the role of the L3 cache. Recall that in the current GPUs based on RDNA 2 architects, the Infinity Cache serves as the L3 cache.
AMD explains in the patent that any interaction between chiplets will be carried out through the active bus, which will be required to access memory channels on separate GPU crystals. Rather than relying on separate caches for each chipset, AMD suggests using the active bus cache as a monolithic GPU cache. In other words, the cache memory will be addressed as a single registry.
AMD’s latest patent, like the previous one, which was reported in January this year, indicates that the company is actively studying the issue of using multi-chip chipset GPUs in the future. True, it is not yet clear whether we are talking only about new generation computational accelerators based on the CDNA architecture or whether AMD is considering using the chipset design in consumer video cards based on the RDNA architecture.
By the way, not only AMD is working in this direction. For example, Intel and NVIDIA have a similar development. The first has a huge multi-chip Xe-HPC, the second has a GH100 ( Hopper ), which is also credited with multi-chip assembly (MCM).
